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Discuss the principle of carry look ahead after and design a 4-bit CLA adder and estimate the speed enhancement with respect to ripple carry adder.
Rajni
on 2011-05-15 09:30:00For each bit in a binary sequence to be added, the Carry Look Ahead Logic will determine whether that bit pair will generate a carry or propagate a carry. This allows the circuit to \"pre-process\" the two numbers being added to determine the carry ahead of time. Then, when the actual addition is performed, there is no delay from waiting for the ripple carry effect (or time it takes for the carry from the first Full Adder to be passed down to the last Full Adder) 4-bit Carry Lookahead Adder For any circuit larger than 4 bits, the Carry Look Ahead circuitry becomes very complicated. For the example provided, the logic for the generate (g) and propagate (p) values are given below. Note that the numeric value determines the signal from the circuit above, starting from 0 on the far left to 3 on the far right: C1 = G0 or P0C0 C2 = G1 or P1C1 = G1 or P1G0 or P1P0C0 C3 = G2 or P2C2 = G2 or P2G1 or P2P1G0 or P2P1P0C0 C4 = G3 or P3C3 = G3 or P3G2 or P3P2G1 or P3P2P1G0 or P3P2P1P0C0 To determine whether a bit pair will generate or propagate a carry, the following logic works: G = A and B P = A xor B (also can be implemented as P = A or B) The Carry Look Ahead 4-bit adder can also be used in a higher-level circuit by having each CLA Logic circuit produce a propagate and generate signal to a higher-level CLA Logic circuit. This becomes very complicated, but the result of having less delay time is very beneficial. For picture - http://www.ict.edu.om/elibrary/engg-ebooks/ebooks/EECP2270-Digital%20Electronics/Book15-WikipediaCom_files/Carry_lookahead_adder.htm
Akshay Kumar
on 2011-05-15 09:30:00suck my ass