Syllabus | Option |
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Syllabus | Download |
Chapter | Option |
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Lecture Notes for Digital Electronics | Download |
Module 1 - Introduction | Download |
Module 3 - Number Base Conversion | Download |
Module 4 - Boolean Algebra and Basic Operations | Download |
Module 5 - Analysis and Synthesis of Combinational Logic Circuit | Download |
Module 6 - Logical Expression Minimization | Download |
Module 7 - TTL | Download |
Module 8 - CMOS Logic | Download |
Module 9 - Memory | Download |
Digital Logic Design by Morris Mano * | Download |
Chapter | Option |
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Introduction To Digital Circuits (49:38) | Watch Here |
Introduction To Digital Circuits (54:27) | Watch Here |
Combinational Logic Basics (49:10) | Watch Here |
Combinational Circuits (53:23) | Watch Here |
Logic Simplification (54:17) | Watch Here |
Karnaugh Maps And Implicants (52:42) | Watch Here |
Logic Minimization Using Karnaugh Maps (52:19) | Watch Here |
Karnaugh Map Minimization Using Maxterms (52:46) | Watch Here |
Code Converters (54:28) | Watch Here |
Parity Generators And Display Decoder (51:26) | Watch Here |
Arithmetic Circuits (52:57) | Watch Here |
Carry Look Ahead Adders (52:40) | Watch Here |
Subtractors (51:00) | Watch Here |
2'S Complement Subtractor and BCD Adder (51:47) | Watch Here |
Introduction to Sequential Circuits (50:24) | Watch Here |
S-R, J-K and D Flip Flops (52:52) | Watch Here |
J-K and T Flip Flops (52:43) | Watch Here |
Triggering Mechanisms of Flip Flops and Counters (52:28) | Watch Here |
Up/ Down Counters (51:33) | Watch Here |
Shift Registers (54:35) | Watch Here |
Application of shift Registers (52:53) | Watch Here |
State Machines (50:15) | Watch Here |
Design of Synchronous Sequential Circuits (53:55) | Watch Here |
Design using J-K Flip Flop (50:55) | Watch Here |
Chapter | Option |
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FULL LENGTH MODEL PAPER | Download |